Computational Hardware Accelerators for Robotics

Computational Hardware Accelerators for Robotics

Project Overview

Computer architects have shown that moving beyond the CPU and GPU, to custom computational hardware, can further accelerate computations while lowering energy consumption. How can we apply these techniques in robotics? This project seeks to answer that question through the design of automated workflows that can directly encode into computational hardware the structured sparsity and parallelism patterns found in embodied robotics algorithms. These resulting co-designed FPGAs and custom ASICs can then be flexibly leveraged for downstream robotics applications.

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