Concepts

The core concepts behind GRiD’s generated code: the design principles, the codegen architecture, the shared-memory resource-tier system, the input/output ABI, and the parallelism patterns.

• Algorithm design principles
  • Summary
  • 1. Smart inners, thin wrappers
  • 2. The inner owns its memory placement
  • 3. Memory-hierarchy design
  • 4. The spill ladder and per-tier picks
  • 5. Adding or modifying an algorithm
  • 6. Validation
  • 7. Anti-patterns
  • Further reading
• Input / Output ABI (h_q_qd_u)
  • The per-timestep input block
  • Floating base
  • Protection by surface
  • Stability
• Library-safe initialization and cleanup
  • The contract
  • Streams, arena and teardown
  • Owning handle
  • Legacy spellings
  • Testing the failure paths
• Runtime contexts
  • The default context
  • Explicit contexts
  • Identity rules
  • Device profile
  • Mutation, model versions and autograd
  • Captured graphs (torch capture / GraphCallable)
  • Synchronisation limits
• Operand validation
  • The rule set
  • Where each surface enforces the rules
• Parallelism patterns
  • P1: level batching of tree recursions
  • P2: parallel independent columns (gradients, Jacobians, Hessians)
  • P3: loop-invariant hoisting with stored temporaries
  • P4: offline memory layout (sparse compaction, coalesced distribution, topology helpers)
  • The parallelism review
• Algorithms
  • inverse_dynamics (RNEA / Recursive Newton-Euler Algorithm)
  • ABA (Articulated Body Algorithm)
  • CRBA (Composite Rigid Body Algorithm)
  • Minv (Direct Mass-Matrix Inverse)
  • Frame Jacobian (general-frame geometric Jacobian)
  • IDSVA / IDSVA-SO (Inverse Dynamics, Second-Order)
  • FDSVA-SO (Forward Dynamics, Second-Order)
  • Kinematics (end-effector pose, Jacobian, Hessian)
  • Bias terms, centroidal quantities and energy
  • Integrators and the plant layer
  • Algorithm Overview
• Codegen architecture
  • The three emission layers
  • Scratch ownership
  • Nested composition
  • Schematic layers (RNEA / inverse_dynamics)
  • Thread-count assumptions
  • Per-algorithm metadata: the descriptor table
  • The binding surface: generated from abi_specs.py
  • See also
• The MuJoCo (mjx) output convention
  • The two raw differences
  • Value and derivative transforms
  • How GRiD serves it: native kernel twins
  • Three ways to request it
  • Build cost and opting out
  • The parity contract
  • Convention map per function
• Resource-tier system
  • Definition
  • Audience and entry points
  • Memory hierarchy: shared versus global, spills, and L2 pinning
  • Block-wide parallelism in the inners
  • Exposed sizing and placement constants
  • Inline-CUDA entry points
  • References
  • Design rationale